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  • What does PHY refer to? - Electrical Engineering Stack Exchange
    I have seen the abbreviation PHY beeing used for a handful of different things within the context of Ethernet: a PHY is a type of Ethernet physical layer (eg 100BASE-TX, 10BASE-T) a PHY is an Ethernet transceiver IC (eg an IC that converts 100BASE-TX to MII RMII) a PHY is a physical layer device (more than just the transceiver IC)
  • ethernet - What is the difference between the PHY sublayers PCS, PMA . . .
    I'm reading Analog Device's Beginner's Guide to Ethernet It's really good and goes into concepts like Manchester Encoding, 4B 5B, NRZT, MLT3 which seem to make sense to me
  • what is the difference between PHY and MAC chip
    A PHY chip or layer converts data between a "clean" clocked digital form which is only suitable for very-short-distance (i e inches) communication, and an analogue form which is suitable for longer range transmission It has no particular clue as to what any of the bits "mean", nor how they should be interpreted or assembled
  • ethernet - PHY address for SPI interface - Electrical Engineering Stack . . .
    The "PHY address" you refer to is an MDIO bus address MDIO is a management interface between a MAC and one or more PHYs In the case of the W5500, the MAC and PHY are integrated in the chip Refer to the W5500 block diagram (green lines added by me): So there's no need for an external management interface, or for PHYAD pins
  • ESP32 GPIO [0] number 2 pin is reserved
    E (111) phy_comm: gpio[0] number: 2 is reserved I'm confused because GPIO 2 is not connected to anything Here is my schematic I have checked the pin physically on the PCB to check any possible soldering mistake that short between the pins and there is none Confirmed with my multimeter
  • phy - RSET pin function of RTL8211E - Electrical Engineering Stack Exchange
    This specific datasheet doesn't specify what the value for the RSET resistor should be But after a bit of looking around, I found another datasheet, page 8 for a Realtek IC (PHY) which uses a bandgap reference as well and they use a value of 2 49k for that resistor The regulator voltages are about the same for both ICs (1 05V vs 1 0V)
  • Connecting a PHY to another PHY on a same board
    Generally, if I'm connecting a PHY to RJ45 connector, I would add center tap capacitors and Bob-Smith termination like below But if I am connecting a PHY to another PHY, do I still need the Bob-Smith termination? Or can I just have center tap capacitors on both sides like below? Both PHYs share same GND but are powered by different rails
  • Ethernet switch IC ports in MAC and PHY mode
    I come from analog RF background and have limited knowledge in digital interfaces According to TI's articles about Ethernet PHY found here and here, single MAC to single PHY connection seems very straight forward You have xMII and MDIO MDC connecting one MAC to one PHY Where I get confused is when an Ethernet switch IC comes into play
  • fpga - Problems in understanding PCIe blocks in Xilinx Vivado for . . .
    \$\begingroup\$ I think that one of the causes of my confusion roots in the definition of PHY: in PCIe standards, the stack layers is usually defined top-down as APP TLP DL PHY, while in IP vendors, the stack layers is usually named as APP CTRL PHY These two PHY are actually different, that IP vendor's PHY is below PIPE interface, only





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